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Table A-7 lists the delays in gross memory access time for several values of VDD IO .
Table A-7. Preliminary Data and Clock Delays
Clock to Address
Worst-Case
VDD IO
(V)
Output Delay
(ns)
30 pF 60 pF 90 pF
Data Setup
Time Delay
(ns)
Spectrum Spreader Delay
(ns)
0.5 ns setting 1 ns setting 2 ns setting
no dbl / dbl no dbl / dbl no dbl / dbl
3.3
1.8
6
18
8
24
11
33
1
3
2.3 / 2.3
7 / 6.5
3 / 4.5
8 / 12
4.5 / 9
11 / 22
The measurements are taken at the 50% points under the following conditions.
? T = -40°C to 85°C, V = VDD IO ±10%
? Internal clock to nonloaded CLK pin delay ≤ 1 ns @ 85°C/3.0 V
The clock to address output delays are similar, and apply to the following delays.
? T adr , the clock to address delay
? T CSx , the clock to memory chip select delay
? T IOCSx , the clock to I/O chip select delay
? T IORD , the clock to I/O read strobe delay
? T IOWR , the clock to I/O write strobe delay
? T BUFEN , the clock to I/O buffer enable delay
The data setup time delays are similar for both T setup and T hold .
When the spectrum spreader is enabled with the clock doubler, every other clock cycle is
shortened (sometimes lengthened) by a maximum amount given in the table above. The
shortening takes place by shortening the high part of the clock. If the doubler is not
enabled, then every clock is shortened during the low part of the clock period. The maxi-
mum shortening for a pair of clocks combined is shown in the table.
Technical Note TN227, Interfacing External I/O with Rabbit Microprocessor Designs ,
contains suggestions for interfacing I/O devices to the Rabbit 4000 microprocessors.
User ’s Manual
79
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